1. Field of the Invention
The present invention relates to etch processes for fabricating integrated semiconductor circuits, Micro Electro Mechanical Systems (MEMS) structures and combined structures having electronics and MEMS.
2. Description of Related Art
As the integrated circuit industry continues to explore techniques to pack more circuits onto a given semiconductor substrate, more and more thought is devoted to orienting devices vertically. One technique of orienting devices vertically is to bury the devices in trenches formed within the face of a silicon substrate. Another technique of orienting devices vertically is to build the devices up from the substrate surface. An example of a device that employs the technique of building devices up from the substrate is a silicon on insulator (SOI) device.
FIG. 1 illustrates a representative mask structure 1 that could be useful in forming an SOI device. SOI devices are characterized by a thin insulative layer of material (commonly referred to in the art as a buried oxide layer) that is sandwiched between the silicon substrate and circuit elements of the device. Typically, no other layer of material is interposed between the buried oxide layer and the silicon substrate. As shown in FIG. 1, buried oxide layer 4 is positioned between silicon substrate 2 and silicon layer 6. Mask structure 1 represents a conventional mask structure used to form SOI devices. As shown in FIG. 1, mask layer 12 is formed over nitride layer 10, which is formed, in turn over oxide layer 8. While specific layer thicknesses vary depending upon application, a representative layer thickness or each layer is (a) about 15,000 xc3x85 for mask layer 12; (b) about 2000 xc3x85 for nitride layer 10; (c) about 10,000 xc3x85 for oxide layer 8; (d) between about 22 to 28 xcexcm for silicon layer 6; and (e) about 5000 xc3x85 for buried oxide layer 4. When pattern structure 1 is etched in accordance with well known etching methods, trenches are formed in silicon layer 6 as the mask pattern is transferred into the silicon layer 6. In accordance with these well known methods, etching of silicon layer 6 continues until buried oxide layer 4 is reached. General requirements for the trenches formed in silicon layer 6 are vertical sidewalls (i.e., sidewalls of about 89xc2x0+/xe2x88x921xc2x0) with minimal erosion of buried oxide layer 4. It is to be appreciated that Mask structure 1 could be formed from a wide variety of materials. For example, mask layer 12 could be formed from an oxide a nitride or a metal. Silicon layer 6 could be formed from, for example, epitaxial silicon, polysilicon, doped polysilicon or amorphous silicon.
The increased use of SOI structures has resulted in a desire to fabricate a growing number of devices and to combine a wide variety of device structures on a single workpiece. SOI is being used to form capacitors, and circuits for high frequency devices such as laptop computers and mobile phones. In addition to an increasing variety of electronics, SOI structures are being utilized to form accelerometers, cantilever beams and other Micro-Electro-Mechanical-System (MEMS) devices that typically incorporate mechanical and electronic components on same device. The increasing variety of structures to be fabricated, and the desire to integrate them onto a single workpiece has lead to increased fabrication complexity.
Referring again to FIG. 1, Mask structure 1 illustrates many of the challenges involved in fabricating complex structures such as, for example, an SOI structure. A first challenge arises from the fact that mask structure 1 can include regions having a variety of critical dimensions, which dimensions range, for example, from sub-micron up to several microns. Regions having small critical dimensions, such as for example small critical dimension region 16, may have critical dimensions on the order of about 0.1 xcexcm to about 0.2 xcexcm. Some regions may have intermediate range critical dimensions, such as medium critical dimension region 18 where critical dimension ranges, for example, from 0.2 xcexcm to about 1 xcexcm. Still other regions may have large critical dimensions such as large critical dimension region 20 where critical dimensions range from, for example, 1 xcexcm to several microns.
A second challenge arises from the fact that mask structure 1 includes regions having varying degrees of line density. Regions of high line density such as high-density region 22 and low line density such as low line density region 26 are present in Mask structure 1. Mask structure 1 also includes isolated lines, such as for example, isolated line 28.
A third challenge arises from the fact that mask structure 1 also includes both high open area percentage structures and low open area percentage structures. Open area percentage is defined as a ratio between an area of silicon to be etched to a total area of the silicon substrate surface. Open area percentage can be measured on a micro level, for example, the open area percentage for a specific die pattern or on a macro level, for example, the overall open area percentage for a number of die patterns distributed across the substrate. Typical design parameters for electronic device applications such as deep trench isolation, power devices. and high frequency silicon on insulator devices call for open area percentages of less than about 20. On the other hand, design parameters for MEMS applications typically have open area percentages of more than about 20 and may have open area percentages as high as about 80. Mask structure 1 represents both low open area percentage regions, such as region 30, and high open area percentage regions, such as region 32.
When epitaxial silicon is used as the silicon layer in an SOI structure, the epitaxial silicon is generally formed by bonding the silicon surfaces of two silicon wafers together and then either thinning or separating the substrates to reveal an epitaxial layer. Various bonding and thinning methods have been proposed and are under development; however, silicon bonding remains an expensive and time-consuming process for obtaining epitaxial silicon. In contrast, deposited silicon, typically polysilicon or amorphous silicon, remains a more economic alternative to the expensive bonded epitaxial silicon techniques. However, the use of deposited silicon is not without problems.
In general, the thickness uniformity of deposited silicon is relatively high, for example, on the order of about 15-20%. For example, a layer of deposited polysilicon with a target thickness of about 26 xcexcm may have areas with thicknesses ranging from about 24 xcexcm to about 30 xcexcm. Variations in thickness can complicate an etch process, and particularly an etch process conducted on complicated structures such as mask structure 1 of FIG. 1. One such complication is notching which is illustrated in FIG. 2. Another complication of continued etching after the removal of the silicon layer is erosion of the buried oxide layer. In spite of these shortcomings, the lower cost, widespread availability and familiarity with silicon deposition techniques and systems, ensures deposited silicon will remain a material of choice in future electronic and MEMS applications.
Etch processes can be categorized as dry or wet. Both types of etch processes are employed in MEMS and electronics fabrication processes. Wet etch chemistry typically involves exposing a structure to a liquid chemical bath containing an etchant solution. Common wet etch processes involve immersing the structure in the etchant containing chemical bath, such as for example a buffered HF solution, until the desired etching is complete.
Dry etch chemistry typically involves exposing a structure a plasma containing an etchant. Common plasma processes for etching silicon typically utilize, for example, a single step, SF6/O2 based plasma, either alone or in combination with a passivating agent such as, for example, HBr, C4F8, CHF3 or CH2F2. A problem common to wet and dry etch methods is an inability to compensate for etch rate variations caused by structural variation (i.e., variations in line density, critical dimension and open area percentage) and layer thickness variations present in a layer of a structure being etched. Variations in structure often result in variations in etch rate. For example, an area with large critical dimensions will generally experience higher etch rates than a region with smaller critical dimensions. In general areas with higher etch rates will etch through a layer and reach an underlying layer in advance of regions having slower etch rates. However, in common etch processes, etch duration is generally determined by the etch rate of the slowest etching region to achieve complete removal of the layer to be etched.
A problem associated with etch duration based on the slowest etching region is that higher etch rate regions will etch through the layer first, and continue to etch, at varying degrees, the surrounding etch layer and the exposed underlying layer. FIG. 2 represents, a portion of an SOI structure 50 having a silicon layer 52 and a buried oxide layer 54 formed on top of a silicon substrate 56. The trench 58 exists in a region with an etch rate faster than the slowest etch rate used to determine the duration of the etch. Since trench 58 is formed in a region having a relatively higher etch rate than the slowest etch rate region, etching will continue in trench 58 to expose buried oxide layer 54. As a result of continued etching after reaching buried oxide layer 54, the bottom of trench 58 exhibits loss of sidewall profile control 60 that is commonly referred to in the art as notching. The resulting sidewall profile created by notching increases the complexity of subsequent deposition operations intended to fill trench 58 often resulting in portions of the notched area not being filled by the subsequent deposition processes. As etching continues in trench 58, the notched region 60 enlarges and buried oxide layer 54 erodes 62 potentially resulting in diminished device performance or failure.
In light of the above, there is a need in the art for an etching method capable of etching a layer in a structure while compensating for etch rate variations that occur between different regions of the structure.
Embodiments of the present invention advantageously provide an etch method which meets the need in the art relate art for an etching method capable of etching a layer in a structure and compensating for etch rate variations that occur between different regions of the structure. In particular, one embodiment of the present provides a method of etching a layer formed over an underlying layer in a structure, the method comprising the steps of: exposing the structure to a first etchant that etches a portion of the layer for a period of time sufficient for a region of the layer with a fastest etch rate to etch through the layer; and exposing the structure to a second etchant that etches a portion of the layer for a period of time sufficient for a region of the layer with a slowest etch rate to etch the layer.